FPGA IP CORES
Intellectual Property Cores for Wide Range of Video Formats and Standards
Intellectual Property Cores for Wide Range of Video Formats and Standards
The AVC Decoder Core is a highly optimized, high resolution decompression engine targeted primarily at FPGAs. It is well suited for various applications ranging from broadcast and professional video to high end consumer electronics.
The decoder design is fully autonomous and does not require any external processor to aid the decode operation. The IO interface comprises of an input FIFO and an output frame buffer. Decoded data can also be provided on a serial bus with embedded sync information. The decoder requires DDR SDRAM to store reference pictures. .
The decoder solution is available either as a FPGA netlist orin source code format and can be customized to meet therequirements of end users.
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COMPLIANCE
HIGH PERFORMANCE
VIDEO FORMAT
INTERFACES
HIGHLY OPTIMIZED
AVC HD decoder is fully compliant with the ISO/IEC 14496-10 & ITU-T H.264 standard. The AVC HD Decoder has been validated in hardware using conformance streams from ITU-T & other Industry standard test suites for functional and performance testing. It is a universal decoder.
This IP is filed, tested and proven in various customer applications. VYUsync’s AVC HD decoder IP core is evaluated & purchased by leaders in Broadcasting Industry. The AVC HD decoder supports all the features which are part of the H.264 standard with respect to the Profiles listed.
The AVC HD Decoder is an Ultra-low latency decoder with robust error handling resilience & Concealment. It support Constrained Baseline, Main & High profiles that allows for a bit depth of 8-bits to 10-bits per sample with support for 4:0:0, 4:2:0, and 4:2:2 Chroma sampling.
The AVC HD decoder is capable of decoding all the bit streams that are encoded for the High Tier & Level 4.1 and for all lower tiers/Levels. The AVC HD decoder supports CABAC Bitrate of 80Mbps and CAVLC bitrate of 160 Mbps. The decoder decodes at the rate of 60 Frames per second.
The video formats supported by the AVC HD decoder are .NTSC, PAL, 720p50, 720p59.94 720p60, 1080i50, 1080i59.94, 1080i60, 1080Psf25, 1080Psf29.97, 1080Psf30 1080p23.98, 1080p24, 1080p25, 1080p29.97, 1080p30, 1080p50, 1080p59.94, 1080p60.
All the non-standard resolutions are supported by the decoder up to a maximum resolution of 1920 x 1080 and a maximum frame rate of 60. For example, monitor resolution 1600x900, 1,280×720 is supported.
The IO interface comprises of an input FIFO and an output frame buffer. The AVC HD decoder accepts Elementary stream in Annex B Byte stream format. There is also an option for accepting Transport stream input when coupled with Transport Stream Demultiplexer IP.
The decoder requires DDR SDRAM to store reference pictures. The decoded pixels are written to DDR4 memory and decoded picture properties are signaled to the external system. The decoded data can also be provided in YUV data with embedded sync information.
The AVC HD decoder can be implemented in the Xilinx Kintex Ultrascale and all 7 and 6 series FPGAs. The AVC HD decoder on Intel Altera devices are also supported. FPGA resources utilization for 1920 x 1080p60, 422, 10-bit, 40 mbps CABAC, 80 mbps CAVLC decoder is LUT’s -33,000, BRAM’s – 91 & DSP’s – 112. This does not include memory controller, display controller & TS demultiplexer
The AVC HD Decoder solution requires a total of 40-bit External memory running at 500 MHz. Typically 64-bit used instead of 40-bit. Memory bandwidth is calculated for the worst case inter prediction scenario where in all images are partitioned into 8x8 blocks which use bidirectional inter prediction.